Yale-IBM collaboration mitigates memory storage problem

A joint collaboration between @Yale and @IBM is investigating how novel computer memory devices may offer optimal information storage. The team, which published its findings in the journal Advanced Materials on Jan. 12, focused on phase-change memory transistors, a class of devices that stores information differently than the Flash transistors typical to common electronic devices. The team’s research focuses on optimizing transistor function. While Flash transistors depend on floating electron gates to encode binary information, a phase-change memory transistor employs a crystalline structure. By using a crystal whose structure changes significantly when heated, researchers can create transistors able to store information even more effectively than traditional Flash transistors. “It’s faster and consumes less power,” said first author Terry Xie GRD ’20, a member of professor Judy Cha’s lab. Because crystals can have varying levels of resistance, a single phase-change memory transistor could potentially store more states than just one and zero, which would improve storage capacities significantly, he noted. Cha, the paper’s corresponding author, said that most computers rely on two types of data storage: fast-acting but volatile memory and slow but secure storage. Because computing is becoming more data-intensive, though, the high price of upgrading memory presents a barrier to improving computing power, she added. Transistors using phase-change memory, or PCM, are attractive candidates for those hoping to create a third tier of computer-data retention beyond memory and storage, called storage-class memory, she said.

https://yaledailynews.com/blog/2018/02/15/yale-ibm-collaboration-mitigates-memory-storage-problem/

Self-Healing of a Confined Phase Change Memory Device : One Step Closer to Storage Class Memory

#Phasechangememory ( #PCM ) devices, i.e. non-volatile, fast switching, long retention time devices, are nowadays envisaged as a revolutionary alternative to conventional computer random-access memory (RAM), expected to meet the growing memory demands of ever-increasing computing power and data-intensive applications. Despite the rapid growth of the field that has allowed the fabrication of confined PCM devices demonstrating more than two orders of magnitude improvement compared to the conventional mushroom cell, the physics that govern the system’s endurance, remain elusive. Fundamental questions related to the observation of the phase change during operation are yet to be addressed, inhibiting therefore our ability to further improve the performance of these systems. Aiming to shed light to this question, recently Xie and co-authors at Yale University and IBM Watson Center, employed in situ transmission electron microscopy to directly observe the phase change of a working device and showed self-healing of novel confined PCM devices by controlling the electromigration of the phase change material at the nanoscale.

http://www.advancedsciencenews.com/self-healing-confined-phase-change-memory-device-one-step-closer-storage-class-memory/

Evolution of Real-Time Applications Calls for Novel Memory Technologies

We are now beginning to see the emergence of a range of technologies that will lead to major changes in the design of real-time embedded systems. These technologies include the Internet of Things ( #IoT), #artificialintelligence ( #AI ) and #augmentedreality ( #AR ). The unifying thread between all of them is a greater focus on the use of distributed systems coupled with a need for high performance to deal with the data they generate and consume. There are tensions that pull the engineering of real-time devices employing such technologies in different directions. Edge devices such as IoT sensor nodes and gateways call for the lowest-power operation. But this is not the only area that needs energy efficiency. Despite their reliance on high-performance graphics and responsiveness to movement, AR-enabled systems (such as head-up displays for machine operators) also have to preserve as much energy as possible, protecting battery life and preventing head-mounted displays from becoming uncomfortably warm. Similarly, versatile robots enabled by AI need to be able to operate away from mains power. Distributed processing allows intensive computational work to be moved to the cloud and so offload the embedded systems. However, the real-time nature of these applications calls for low latency. Applications such as motion control and AR suffer if the delay from input to response is too long. This issue is leading to the deployment of edge computing server or ‘cloudlets’ - efficient server blades located relatively close to the edge devices themselves. To support real-time applications such cloudlets are in a position to take advantage of changes in memory technology to better fit the real-time nature of the clients they serve than traditional server designs. Historically, engineers have been forced to choose between performance and persistence when designing bulk memories into real-time computer systems. DRAM is cost-effective for storing large amounts of data close to the processor but is volatile. To ensure data is not lost through power issues - which are more likely to occur in edge nodes - data often has to be copied to persistent storage, which have often much slower access times. The move from rotating disk drives to flash memory for larger applications has already helped significantly when it comes to read access times. But flash still has its drawbacks when it comes to write performance. The erasing and rewriting of data from/to flash memory takes multiple cycles during which high-voltage pulses are delivered to the target memory cells. That takes both time and energy that system designers do not want to waste. Next generation memory technologies are now appearing that overcome the write delays and power demands of flash. These technologies include #ferroelectricmemory, #phasechangememory ( #PCM), #magneticrandomaccessmemory ( #MRAM) and #resistiverandomaccessmemory ( #ReRAM). As devices based on these concepts become available, engineers can consider using them in novel memory hierarchies that optimise cost, increase resilience and improve real-time responsiveness. PCM was first put forward as a possible memory material as long ago as the 1970s. It is based on the same group of chalcogenide materials as those used in rewritable optical disks. A useful feature of the chalcogenides is the way they react to heat. High-current pulses will melt the material. If left to cool quickly it turns to a resistive amorphous state. But the amorphous state can be converted to a crystalline form with a much higher conductivity by applying a small amount of heat. Thanks to this change in properties, readout circuitry can interpret the difference in resistivity between cells as representing ones and zeros. Though similar in behaviour to PCM, with the same core approach of switching between high-resistance and low-resistance states, ReRAM uses different materials to chalcogenide. Typically, the movement of ions within the cell under the influence of pulses of current forms conductive filaments. Reset pulses disrupt these filaments, greatly increasing resistance. One potential advantage of ReRAM is that a large number of candidate materials could be chosen to implement them. This provides the scope for manufacturers to introduce memories with different levels of resilience and storage time. Although these memories use current pulses, the total charge required to program a cell is much lower than that required for flash. In the memories being developed today, ReRAM requires less write energy than PCM but the write times are similar. However, endurance is better in PCM than ReRAM and PCM currently lies further ahead on the development path. Experts believe both PCM and ReRAM will scale better than flash in the long term and so could ultimately supplant flash entirely. Ferroelectric memory and MRAM use the spin properties of electrons for storage. The spin can be controlled with very little energy through a spin-valve structure similar to that used in high-density read heads for magnetic disks. In an MRAM, this spin valve is made from a sandwich of materials formed in a via that lies between two metal interconnect lines on the surface of an integrated circuit (IC). The valve alters the resistance of the via based on the spin states of different materials in the sandwich. Ferroelectric memory has been available for several decades but in comparatively low densities to those envisaged for the resistance-based memories. Ferroelectric memory requires both a capacitor and transistor to be formed on the base layer of the wafer. The other memories are all formed in the metal interconnect layers and, potentially, can be stacked for higher integration. A key advantage for ferroelectric memory is its use of materials that polarise in two different directions based on an applied electric field. This polarisation requires even less power than is needed for MRAM, which makes it suitable for systems that need to be highly energy efficient. A potential problem for all the novel memories today is that they lack the cost-effectiveness and density of flash, which is now beginning to take advantage of 3D manufacturing techniques. In reality, for cloudlets and also edge devices themselves, the density is not a major issue as these memories can serve as the underpinning for persistent caches. The low-power and relatively fast write times of the novel memories provides applications with the ability to copy important data to the persistent cache. Data objects that need to be stored permanently can, from there, be copied to flash or disk storage. However, there is no longer any need to transfer data to flash or disk storage continually just to ensure that important but transient data is not lost. When the system restarts, it can recover its state from combining data in both the permanent and persistent arrays. As costs come down and performance improves, there is the potential for MRAM, PCM or ReRAM to begin to displace DRAM and so move the architecture to one in which only the caches on the processors themselves employ a volatile memory architecture (such as SRAM). Persistent memory technologies need not be isolated to cloudlets and high-performance systems. The use of ferroelectric memory by Texas Instruments in its MSP430 line of microcontrollers provides an example of the impact it can have in IoT edge nodes such as sensors. Many IoT applications will rely on energy harvesting to at least supplement a built-in battery. Some may dispense with the battery altogether. The problem with energy harvesting is one of reliability. There are situations, such as vibrational energy capture on heavily used industrial machinery, where the power source is predictable. But in many cases, even with the use of a supercapacitor for an energy reservoir, the system may run temporarily short of power and need to shut down. When enough external energy is supplied, it can resume normal duties. The use of ferroelectric technology provides the microcontroller with the ability to ensure data persists through unexpected power outages without incurring an energy penalty even when data is written to it frequently. Although applications area, such as the IoT, AI and AR, will radically change real-time system architectures, new memory technologies will be able to address these demands accordingly. Through the development of MRAM, PCM, ReRAM and ferroelectric memories it will be possible for system designs to support the responsiveness and cost-effectiveness required.

https://www.google.com/url?rct=j&sa=t&url=http://www.newelectronics.co.uk/electronics-technology/evolution-of-real-time-applications-calls-for-novel-memory-technologies/167221/&ct=ga&cd=CAEYACoUMTQ1NTM4MzM4MzcxNzE0NTkyNDAyGmFmMWQ2ZWJlOWM3NGYzNTk6Y29tOmVuOlVT&usg=AFQjCNEQX08rNWOr5tlPh9oAi7XWY04dLw

A New Memory Contender?

Momentum is building for a new class of #ferroelectricmemmories that could alter the next-generation memory landscape. Generally, ferroelectrics are associated with a memory type called ferroelectric RAMs ( #FRAM s ). Rolled out by several vendors in the late 1990s, FRAMs are low-power, nonvolatile devices, but they are also limited to niche applications and unable to scale beyond 130nm. While FRAMs continue to ship, the industry has also been developing a different memory type called a ferroelectric FET (FeFET). Instead of using traditional FRAM materials, FeFETs and related technologies harness the ferroelectric properties in hafnium oxide, sometimes referred to as ferroelectric hafnium oxide. (FeFETs are different than a logic transistor type called finFETs). Still in the R&D stage, a FeFET isn’t a new device, per se. For FeFETs, the idea is to take an existing logic transistor with a high-k/metal-gate stack based on hafnium oxide, and then to modify the gate insulator with ferroelectric properties. The resulting structure is the same transistor with a scalable, embedded FeFET memory with low-power and nonvolatile properties. In theory, that should outperform today’s embedded flash memories. Fig. 1: How to make a FeFET. Source: Ferroelectric Memory Co. Others are working on different types of FeFET-based, nonvolatile devices. It sounds like a simple concept, but there are several challenges, such as integration issues, data retention, reliability and cost. “(FeFETs are) promising, but it’s still early,” said Greg Wong, an analyst with Forward Insights. There are other challenges as well. “For a new emerging memory technology, the toughest part is to get credibility and confidence on the customer side that your solution is real,” said Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), a startup that is developing FeFETs. Still, FeFETs and related technologies are gaining steam. Here are the most recent developments in the arena: • GlobalFoundries, FMC, NaMLab, Fraunhofer and others have reached a major milestone by demonstrating an embedded, nonvolatile FeFET in a 22nm FD-SOI process. The technology is slated for qualification in 2019, although there is no timetable for production. • Imec is developing a scheme that would replace current DRAM materials with ferroelectric hafnium oxide, creating a new class of nonvolatile DRAM-like memories. In addition, Imec is also developing a stacked ferroelectric device that resembles a 3D NAND. • SK Hynix, Lam Research, Versum and others recently presented a paper on the switching mechanisms of such devices, of which the group calls a 1T-FeRAM and a 3D FeNAND. • A growing number of groups are exploring ferroelectric hafnium oxide for a next-generation logic transistor type, commonly referred to as a negative-capacitance field-effect transistor (NC-FET). NC-FETs are a potential transistor candidate for 3nm and beyond. 3D FeNAND, ferroelectric DRAMs and NC-FETs are still in the early stages of R&D, and it’s too soon to say if these technologies will ever make it into production. The big proving ground is the FeFET being developed by GlobalFoundries, FMC and others. If it flies, the FeFET joins a crowded field in the next-generation memory market. Other new memory types, such as 3D XPoint, Magnetoresistive RAM, ReRAM and even traditional FRAM, are shipping. Potentially, FeFETs will compete with some but not all of these technologies. Next-gen memory race For years, the industry has been developing the next-generation memory types and for good reason—the traditional memories have an assortment of limitations. For example, DRAM, which is used as the main memory in systems, is fast and cheap. But DRAM is volatile. It loses data when the power is turned off in a system. NAND and NOR flash memory are also cheap. Flash is nonvolatile and stores the data even when the power is off. In operation, though, flash undergoes several read/write cycles, which is a slow process. This is where the new memories fit. Generally, the next-generation memory types are fast, nonvolatile and provide unlimited endurance. They also provide bit-alterable, erase-free functions, making them potentially ideal replacements for DRAM and flash. But these new memories also rely on exotic materials and complicated switching mechanisms, so they have taken longer to develop. At the same time, the industry continues to scale DRAM and flash, making it difficult for the new memory types to get a foothold in the market. Still, the industry is beginning to ramp up some of the new memory types. Here is a simple explanation of the landscape: • Intel and Micron are ramping up 3D XPoint, a next-generation technology based on phase-change memory. 3D XPoint is a standalone device, which is used to speed up the operations in a solid-state drive (SSD). • Everspin and others are developing a next-generation MRAM technology called spin-transfer torque magnetoresistive RAM (STT-MRAM). Used for embedded or standalone applications, STT-MRAM uses the magnetism of electron spin to provide nonvolatile properties in chips. • Several vendors and foundries are developing resistive RAM (ReRAM) for standalone and embedded apps. In ReRAM, a voltage is applied to a material stack, creating a change in the resistance that records data in the memory. • Cypress, Fujitsu, Panasonic, TI and others are shipping microcontrollers (MCUs) with embedded FRAM. Fig. 2: Spin torque MRAM technology. Source: Everspin Fig. 3: ReRAM in action. Source: Adesto FRAMs are widely misunderstood, as ferroelectric materials are not ferromagnetic. “[Ferroelectric memory] writes an application using an electric field only and no current flow,” FMC’s Müller explained. “All of the other emerging memory concepts, like resistive RAM, phase-change memory, and MRAM all write by driving a current through the memory cell.” The FRAM is based on a(one transistor, one capacitor (1T-1C) storage cell design. Using a ferroelectric capacitor to store data, FRAM is a low-power, nonvolatile memory with unlimited endurance, making it ideal for various embedded chip applications. Typically, FRAMs consist of a thin ferroelectric film, based on lead zirconate titanate (PZT). “The atoms in the PZT change polarity in an electric field, thereby producing a power efficient binary switch,” according to Cypress. Fig. 4: Traditional FRAM. Source: Cypress FRAMs have some issues, however. “The classical FRAM is exotic from the materials point of view,” Müller said. “FRAM has not scaled beyond the 130nm technology node due to the fact that only planar capacitors can be used and the traditional ferroelectric films are not scalable. This has prevented traditional FRAM from widespread adoption.” With FeFET, which is different than traditional FRAM, proponents hope to solve these issues. Several years ago the industry stumbled upon a new discovery, namely the ferroelectricity properties in hafnium oxide. Researchers discovered a crystal phase can be stabilized in the process of doping hafnium oxide. “Within that crystal phase, the oxygen atoms of hafnium oxide can reside in two stable positions, shifting either up or down according to the polarity of an externally applied electric field,” according to FMC. Hafnium oxide is a well-understood material. For some time, chipmakers have used hafnium oxide as the gate stack material for high-k/metal-gate structures in logic devices at 28nm and beyond. For FeFETs, the idea is to leverage properties of ferroelectric hafnium oxide rather than to create a new device architecture using exotic materials. In FMC’s technology, for example, the ideal is to take an existing transistor. Then, using a deposition process, a silicon-doped hafnium oxide material is deposited into the gate stack of the transistor, creating a ferroelectric property. FMC’s scheme also eliminates the need for a capacitor, enabling a one transistor memory cell or a 1T-FeFET technology. “In FeFETs, a permanent dipole is formed within the gate dielectric itself, splitting the threshold voltage of the ferroelectric transistor into two stable states,” Müller said. “Accordingly, binary states can be stored in the FeFETs similar to how it is done in a flash memory cell.” Fig. 5: FeFET (n-type functionalty). When the ferroelectric polarization points downward (left), electrons invert the channel region, permanently bringing the FeFET into the “on” state. If polarization points up (middle), permanent accumulation is created and the FeFET is in the “off” state. Source: FMC. In theory, the technology is compelling. “You have hafnium oxide in every cutting-edge transistor. It’s the gate dielectric,” he said. “If you do it cleverly and modify the hafnium oxide, you can actually transition your logic transistor, which loses a state when you remove the power, into a nonvolatile transistor. It remains in state when the power is removed.” FeFETs are still in R&D and not ready for prime time. But if it does work, customers would have yet another choice in the next-generation memory world. 3D XPoint, FRAM, MRAM, ReRAM and others are also in the arena. So which new memory technology will prevail? That’s not entirely clear, because no one memory can handle all requirements. Each new memory type has its place. And the new memory types are taking some sockets away from traditional memories. But by and large, traditional DRAM and NAND continue to dominate the memory hierarchy. Fig. 6: Memory hierarchy Source: Imec Embedded memory wars In the memory space, the emerging battle is taking place in the embedded market. Today’s MCUs integrate several components on the same chip, such as a CPU, SRAM and embedded memory. The CPU executes the instructions. SRAM is integrated on the chip to store data. Embedded memory, such as EEPROM and NOR flash, are used for code storage and other functions. “With EEPROM, each bit is two transistors. And each byte can be erased or re-programmed,” said Jim Handy, an analyst with Objective Analysis, in a recent interview. “On each block (with NOR flash), we have one huge transistor that does the erase for all of the bits on the block. A huge transistor still saves a lot of chip space, compared to two transistors per bit.” Embedded flash (eFlash) is robust, making it ideal for industrial applications. For example, automotive OEMs have stringent requirements and NOR fits the bill. “Performance-driven automotive MCUs are a driving force behind eFlash,” said Walter Ng, vice president of U.S. sales at UMC. NOR has some limitations, as the write speeds are slow. NOR is also becoming more expensive as it moves from 40nm to 28nm. And it’s unclear if NOR can scale beyond 28nm. Suppliers of next-generation memories hope to fill the void. “Emerging RAMs seemingly provide a possible solution,” Ng said. “Yet, it remains to be seen how such technologies will be received by the automotive community.” Regardless, the embedded memory market is heating up. Several foundries—such as GlobalFoundries, Samsung, TSMC and UMC—are developing embedded STT-MRAM. In addition, SMIC, TSMC and UMC are developing embedded ReRAM. FeFET is the new kid on the block. In 2009, Fraunhofer, GlobalFoundries and NaMLab began to explore FeFETs. Later, FMC was spun out of NaMLab. In 2014, the group demonstrated a simple FeFET array based on a 28nm CMOS process. Then, at the recent IEDM conference, GlobalFoundries, Fraunhofer, NaMLab and FMC presented new results that brought FeFETs one step closer towards commercialization. The group demonstrated an embedded FeFET in a 22nm FD-SOI process. “It’s a very low-cost approach for getting a very dense type of memory,” said Gary Patton, CTO at GlobalFoundries. The FeFET, according to the IEDM paper, has a cell size as small as 0.025μm². The device consists of a 32MBit array with program/erase pulses in the 10ns range at 4.2 volts. It has a temperature retention rate up to 300 °C. Initially, FeFETs are targeted for the embedded nonvolatile memory market for consumer applications. “It is around two orders of magnitude faster in write (than traditional eFlash). We write in the 10ns regime, where flash writes in the 1ms to 10ms regime,” FMC’s Müller said. The technology is promising. “They are farther along than anyone else,” said Jan Van Houdt, a distinguished member of the technical staff at Imec. “They are going for the embedded case right away. It’s probably going to work.” FeFETs face an uphill battle in embedded memory space for automotive, where the temperature requirements are more stringent. Automotive OEMs, though, are indeed looking at STT-MRAM, as the technology can withstand higher temperatures. What’s next? For its part, Imec is developing ferroelectric technology on two fronts. One involves a new type of a nonvolatile DRAM-like device, while the other is a standalone storage device that resembles 3D NAND. DRAM is based on a 1T1C cell structure. In operation, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the capacitor must be refreshed every 64 milliseconds, which, in turn, consumes power in a system. Inside DRAM’s vertical capacitor structure, there is a metal-insulator-metal (MIM) material stack. In the MIM stack, a high-k material is sandwiched between two zirconium dioxide layers. This is sometimes called the ZAZ capacitor. Imec and others are exploring the idea of replacing the zirconium dioxide material with ferroelectric hafnium oxide in the DRAM. Hafnium oxide in its ferroelectric state is similar to zirconium dioxide. With the technology, Imec is developing a ferroelectric DRAM-like device with nonvolatile properties, which does not require a refresh operation. There are challenges, of course. Scaling the vertical 1T1C capacitor is difficult for DRAM at each node. That won’t change for a ferroelectric DRAM-like device, as the device is also configured with a 1T1C cell. Fig. 7: DRAM roadmap Source: Imec Another possibility is that the industry could develop a one transistor (1T) DRAM-like device with nonvolatile properties. That is a capacitor-less ferroelectric DRAM-like device. But even with ferroelectric hafnium, ferroelectric-based DRAMs face some challenges. “The problem is that it has some endurance limitations. DRAM almost has unlimited endurance. With ferroelectrics, that has to be proven,” Imec’s Van Houdt said. Imec also is pursuing a ferroelectric device technology that resembles a 3D NAND. The technology, sometimes referred to as a 3D FeNAND, is built using a 3D NAND-based manufacturing flow. “It’s low voltage and nonvolatile. Power consumption is much lower. It would be faster, because it’s a high-k material. So your transistor is going to drive much more current than NAND,” Van Houdt said. The problem? “It’s sort of a NAND replacement. But, of course, to replace NAND is almost impossible,” he said. So if it does fly, the device could fit somewhere in the storage-class memory hierarchy. But the technology is still five to ten years away from entering the commercial market. There are other issues. For example, in a paper at IEDM, SK Hynix, Lam and others found that the actual switching speeds are slower than expected in ferroelectric hafnium oxide materials due to extrinsic disorders. SK Hynix, Lam and others found a way to control the grain size of the silicon-doped hafnium oxide, which in turn boosts the speed of the material set. “We successfully demonstrated that Si:HfO2 consists of controlled nano-grains with a FE property of Ec ~0.5MV/cm, which is a half of the ordinary Si:HfO2, and the domain switching speed reaches ~3 times faster than that of ordinary grain sized Si:HfO2,” according to the paper. What are NC-FETs? There are other applications for ferroelectric hafnium oxide. For some time, University of California at Berkeley and others continue to pursue the NC-FET, a next-generation logic transistor targeted for 3nm or beyond. Like the FeFET, the NC-FET isn’t a new device. In NC-FET, the gate stack in an existing transistor is modified with ferroelectric hafnium oxide. The film thicknesses are slightly different in an NC-FET as compared to a FeFET. “That’s why there is so much keen interest,” said Mike Chudzik, senior director of the Transistor and Interconnect Group at Applied Materials. “It’s a simple swap of a dielectric for a ferroelectric. I would put it alongside tunnel FETs.” NC-FETs are steep sub-threshold slope devices for low-power apps. It would compete more with a tunnel FET (TFET), a low-power transistor type aimed for 3nm and beyond. “Essentially, a ferroelectric is like a voltage amplifier. You put one voltage on it. Because the way it interacts, it amplifies the voltage. That’s why you get this enhanced sub-threshold slope,” Chudzik said. With the technology, UC Berkeley is exploring the idea of extending today’s finFET and FD-SOI technologies down to 2nm. UC Berkeley refers to its technologies as NC-finFET and NC-FD-SOI. To be sure, the NC-FET is still in the early stages. “There is a lot of promise and interest in it, but there are a lot of unanswered questions,” Chudzik said. In the short term, though, the FeFET is the first technology that could appear from the promising material set. This, in turn, could set off a wave of R&D in the arena. Or, like other technologies, it could simply fall by the wayside.

https://semiengineering.com/a-new-memory-contender/

7 Tech Predictions For 2018 And Beyond

The technology trends of 2017 were big and impactful, with #ArtificialIntelligence ( #AI ) and many self-service platforms enhancing human experience. Today technology helps people and businesses accomplish so much more than they could even think a decade ago. Technology is evolving and meshing up into business processes and everyday lives seamlessly. As technology reaches a newer level, we can expect the following trends in the coming times: Integrating New Data into Existing Data Streams From wearables to facial and voice recognition, there are new types of data that can provide insight which haven’t been utilized yet. Integrating a wide range of datasets into marketing campaigns can drive customer signups, lead generation and sales. Companies can integrate new data streams from activity trackers, gym networks and grocery stores to reward customers for loyalty. This new data can also help correctly time tailored notifications, messages and promotions across platforms for consumers. IoT is no longer about Things The convergence of the digital and physical worlds makes it inevitable to stay connected. Businesses harnessing the power of IoT, will gradually shift from product-centric to service-centric business models to deliver convenience to customers throughout the product’s life cycle. Companies selling products will also become service- oriented as their business value moves from products to the enhanced customer experiences they enable. This inclusion of IoT will fundamentally change how businesses operate, interact with customers and earn profits. In the coming times, internet of things will not just be about things but about services positioned to meet newer customer demands and will unlock new sources of revenue. 360-degree Videos and Augmented Reality for 2018 Pokémon Go feels like years ago now, and Augmented Reality is ready to move on to the next level. we have seen a surge in many apps with AR launched in 2017 and there will be more to come in 2018. Apple has built-in support for augmenting whatever the phone’s camera captures with additional information. This means that AR is suddenly within the reach of hundreds of app developers as well as customers. Expect to see VR, AR and 360-degree videos as the next tech trend to become popular since they can be great medium for showcasing or previewing your products and services or encourage product trials. 360-degree Video is becoming the most popular, quick and influential form of digital content for businesses today. Wearable wallet on your wrists In 2018 a growing number of our devices can become payment devices - car keys, vending machines, smart phones, connected cars, sports watches etc.  Artificial Intelligence and IoT will generate intelligent and personalized context-aware customer services, enabling more tailored solutions to help customers make better financial decisions and help companies reduce their operational costs. In 2018, several new device payment systems can be expected, you may have your wallet on your wrists or controlling payments remotely from your wearables. Self-driven cars on the roads Well, thanks to what technology and artificial intelligence has brought to the table, we have got the self-driving car concept. The concept of self-driving cars is still being developed by companies like Google and Tesla Motors, but significant progress has been made so far. But sooner, we may get to see them in commercial use. The idea of self-driving cars revolves around eliminating the human factor in driving, reducing the driving stress and thus reducing the number of traffic accidents and traffic jams. Your assistant isn’t virtual anymore Now it’s time to explore another form of User Interface that might feel even more natural and intuitive: speech. We already have experienced speech recognition- whether it’s in the form of iPhone’s Siri, Android’s Google Now, or Windows Cortana. These services are designed to let you interact with your phone and satiate all your leisure, digital or informational activities. It’s an amazing feat of engineering, but it may not be quite perfect. But with great innovations happening with microchips and cloud computing, we can expect virtual assistants to become frighteningly accurate soon. In the coming times, you may imagine your virtual assistants to understand your speech perfectly, understand the context behind the questions you ask; they will recognize the indirect signals given off by your tone of voice; they will even engage in long form conversations with you Data storage innovations in the pipeline There are limits to the capacity we can squeeze into and the performance we can squeeze out of traditional hard disks using existing designs and manufacturing processes. But to our relief, science is coming to the rescue. A few near- and long-term innovations will be done by hard disk drive manufacturers to satisfy our storage-hungry society. Better hard disk drives, Solid state hard drives, #PhaseChangeMemory ( #PCM ), #ResistiveRandomAccessMemory ( #RRAM ) and #3Dflash memory will bring in the next generation of #datastorage to offer more memory capacity, speed, endurance and power efficiency. These innovations will take by storm the data storage industry and will create the need to shift to cloud based platforms

http://www.cxotoday.com/story/7-tech-predictions-for-2018-and-beyond/

The Next 5 Years Of Chip Technology

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments. What follows are excerpts of that discussion. L-R: Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt. Photo credit: Coventor, a Lam Research company. SE: Looking beyond 10/7nm, is it going to be a straight line to 5nm and 3nm? Is it going to be more difficult than we expect? And is it even going to be possible? Dougherty: It’s possible, and we’ve proven at multiple points in our history that it’s always possible, even if we don’t quite know how. We’ve always found a way through a variety of approaches, and I anticipate the same thing moving forward. I don’t anticipate it will be a straight line, though. It won’t be a hyperbola or an exponential line. We will get there, and there will be a variety of things the industry will uncover. Gottscho: I agree. The path to 5nm is pretty clear. FinFETs will get extended at least to 5nm. It’s possible they will get extended to 3nm. And there will be some other solution after that, whether that’s gate-all-around horizontally or vertically. There will be new materials. There also will be a lot of challenges. We know how to fabricate fins that are 150nm tall with 5nm design rules. Fabricating them is one thing. Preventing them from collapsing is a different challenge. There are a lot of challenges, but I don’t have any doubts this industry will get there, and I don’t think it will be significantly delayed. Shortt: About 30 years ago I first read an article explaining very clearly why we could never possibly make a device smaller than the wavelength of light using imaging. We all know how that turned out, and everyone who bet against optical lithography has been wrong. It always seems like you can’t project more than a couple generations out, but we always seem to be able to do it. As an inspection person, I’m astonished these devices are manufacturable. With 3D NAND, it’s astounding that we can make those. Zhang: We are hearing from our customers on the supply side that scaling has not ended yet. In terms of lithography, we are driving that very hard with EUV at new nodes, with high-NA as an extension to that on the roadmap. So in terms of printing and patterning, we do have solutions out there. There is more of a challenge in how we manage the complexity and the cost. But we will get there. Wolfling: I agree. Complexity is the key here. And the issue is really to work that in more than one way. There is room to extend finFETs. After that it will be nanosheets. Where will be the crossover? Will it be at 3nm or 2nm? At some point the industry crosses over. This is happening with EUV. It will happen with finFETs. The question is where it will happen. SE: We have some big evolutionary problems to solve, though. There are interconnects, RC delay, and a bunch of issues that no one has ever been able to solve. Is this time different, particularly for logic, both from the manufacturing and from the measurement side? Dougherty: The challenge that I see is actually the number of options. The technology we use to scale has expanded. If you go back several generations, you more or less knew the materials and basic structure you were going to use. Now, as you look ahead to 7nm and beyond, our supplier roadmaps say it could be any 1 of these 10 things. The answer is some combination of them, but there’s a lot more work that has to be done to screen down these various options at advanced nodes. We’re getting to the point where it may not be a single solution. For the longest time in this industry, everyone kind of aligned at the end of the day on the same solution. It’s possible there might be some divergence, like back-end-of-line metallurgy. Zhang: The problem is not that you will hit the wall, but that you have many roads. The question is how we explore all of them. In the beginning they can be promising, but it’s difficult to say which one will be cost-effective and which one will be manufacturable. That’s part of the investment that is required—to investigate the different materials and the different directions. I don’t think the problem is that we’re facing a wall. SE: No, but we are facing a lot of choices, right? Gottscho: But with back-end-of-line, at least in the near term—it’s a couple generations out yet—there’s a real opportunity to lower the resistance just by getting rid of the barrier. That’s easy to say, not so easy to do. But when you look at the space occupied particularly vias, it’s dominated by highly resistant material that’s serving as a diffusion barrier. If we can solve that material problem, that will buy us a couple generations at the back-end of line. The contact resistance also is a huge problem, but that’s an example where people have been very creative with an architecture that uses wrap-around contacts, high-dose surface doping, and taking special care for interface properties. These problems are hard, and I don’t doubt there will be at least a couple different solutions. I am curious about metrology, though, because that is often a gate for process development. Zhang: We were talking earlier about measuring something below an Angstrom. We are able to do that now in 3D. So metrology-wise, we do have solutions available. Whether we have solutions for everything we want to measure, that’s still a question. Shortt: What I’ve seen over the years is that the length of time it takes for end-to-end cycle time, from concept to actually shipping, has gotten longer. What we find is that we need to start earlier. We have multiple generations leapfrogging each other, and multiple generations under development at any one time. We have a number of good ideas, but we have to start earlier thinking about them and doing the technical risk reduction to figure out what works and what doesn’t—and get rid of the stuff that doesn’t work and then keep going. So the full end-to-end cost is increasing for us for inspection and metrology. But with proper management, you do the technical risk reduction at the beginning, quickly throw away the ideas that don’t work, and then keep the ones that do. SE: Another piece of logic involved in all of this is 3D NAND. We’ve already scaled up to 48 layers. Does this just keep scaling up, or are there physical limits here? Gottscho: It keeps going up for awhile. I’m pretty optimistic about the future. I don’t think you can be in the semiconductor business and not be optimistic. We see a path to 256 layers. It’s going to be very challenging to go beyond that. But there are a lot of challenges to even get to 128 layers. Stress in the films is a big deal. If wafers come out looking like potato chips, that’s not good. And when you’re trying to stack one layer on top of another, that stress becomes a big problem in terms of distortion and overlay. One of the biggest problems is etching the memory holes. This is the most challenging etch I’ve seen in my 35 years in the etch business, with alternating layers of oxide and nitride, or oxide and poly, with aspect ratios approaching 100:1. But having said that, we have a solutions road map and we’re working on three generations of technology at the same time. It’s going to scale over the next 10 years. Shortt: Do you see the future of 3D NAND doing that etch for 100 layers all in one step? Gottscho: It will be a mixture. Our strategy is to push the etch technology to the highest aspect ratio that it will go, because we believe it’s in our customers’ interest to do as many layers as you can in one pass. But whether you stack 48 or 96 or 128, sooner or later you’re going to want to push out that choice of how many layers you’re going to stack as far as possible. Wolfling: Once you start stacking, if you have three or four more generations and you stack four of them together, it’s not cost-effective. The more you can push the etching, the more you buy time for this direction. SE: The other critical piece of the von Neumann architecture is DRAM. Can we go further with 1x technology to 1y, or do we need to move to some other technology such as phase change memory or STT-RAM? Zhang: Our customers are marching down the path of 1x, 1y, 1z, and trying to squeeze out another nanometer. That’s been the case in the past couple years, and that will continue. As to how far we will go with that, we haven’t really seen another device on the horizon that will replace DRAM. We do see XPoint coming up as another viable memory solution that could be inserted into the current memory architecture. It will be interesting to see how that plays out versus DRAM. Dougherty: But do you think it’s a matter of time with some alternative? There’s certainly a lot of work being done on all these different memories, though we don’t know what the intersection point is. Zhang: That’s why folks are working on XPoint and other memories and seeing how far they can push that from a cost, performance and endurance standpoint. How that can match up to DRAM levels remains to be seen. Shortt: We saw predictions at KLA-Tencor that 3D NAND would have taken over earlier, but with 3D NAND they were able to push that another generation or two beyond what a lot of people expected. That delayed the onset of 3D. The same will happen with DRAM. They’ll push it as far as they can. Gottscho: I see a difference between DRAM and the 2D/3D NAND dynamic in the sense that 3D NAND was ready before 2D NAND ran out of gas. Right now it doesn’t appear as if there is a replacement for DRAM. Whether it’s STT-RAM or phase-change memory or resistive RAM, none of them can match the speed or endurance of DRAM. Necessity is the mother of invention, and we see at least two more generations after 1x. We are hearing about 1a. DRAM still has life in it, but it’s getting tougher. MRAM will probably come in as an embedded memory element in logic. It doesn’t look like a viable replacement for high-density DRAM. Shortt: We’re also not seeing a lot of demand for yet for inspection of these new structures. You would think we’d see that early. We’ve seen a little bit, but not much.

https://semiengineering.com/the-next-5-years-of-chip-technology/

Time to Look For Low-Cost DRAM Alternatives

#DRAM is turning into a seller's market, and it's time to look at low-cost alternatives. DRAM prices are heating up, and there is no easy solution to relieve this high price issue because it does not come from the imbalance between supply and demand, but instead from the end of #MooresLaw for planar DRAM (see related article, Why Memory Prices Are Heating Up). This year, bit growth of DRAM will be the strong 23 years. Planar DRAM scaling has also slowed considerably in the last three years, as shown in figure 1. Therefore, DRAM is transforming into a seller’s market and DRAM vendors are making record profits this year. Similar to oil crisis, customers are paying more for DRAM under the DRAM crisis. Therefore, I would like to discuss what kind of solutions we could find for low cost DRAM.   ADVERTISING  Figure 1: DRAM Roadmap Plan vs. Reality and DRAM ASP For the time being, emerging memories such as MRAM and phase-change memory (PCM) have been challenging planar DRAM. However, MRAM goes to embedded applications and PCM (i.e. 3D XPoint) is being used as high-end SSD applications. Realistically, it is difficult for them to directly replace planar DRAM considering cost-per-bit, performance and reliability. Thus, emerging memories are searching for their own niche market segments now. DRAM fab expansion is one method to increase DRAM supply. However, DRAM vendors may be hesitant because the cost of a new fab is about six times higher than a fab upgrade. For the time being, DRAM vendors have increased DRAM output though fab upgrades for the lateral scaling of DRAM, which increased DRAM bit output exponentially by a power of two. In contrast, a new fab without lateral scaling would require signficantly more investment for just a linear increase in DRAM bit output, which, coupled with higher manufacturing costs, will make DRAM more expensive. Additionally, in a seller’s market, it would be difficult for DRAM vendors to have strong reasons to increase DRAM fab capability through new fab investment without lateral scaling. So, switching from planar DRAM to 3D DRAM is necessary. As shown in the figure 2, more die-per-wafer could be produced using 3D DRAM. As long as the wafer processing cost of 3D DRAM is reasonable, and it is easy to generate 3D DRAM, it is beneficial to adopt 3D DRAM technology for low cost (see related article, Why 3D Super-DRAM). Certainly, 3D DRAM is crucial for the continuation of DRAM scaling. But, unfortunately, DRAM vendors do not have their own 3D DRAM technologies yet.  Figure 2: 3D DRAM enables more die-per-wafer and low cost DRAM Another suggestion is DDR4 NVDIMM to replace DRAM as a main memory. There are many kinds of NVDIMMs. Unlike other storage-oriented NVDIMM, DDR4 NVDIMM should be as fast as DRAM and work as a main memory. Intel 3D XPoint suggested DDR4 NVDIMM a few years ago. Because 3D XPoint has NOR-type flash, it could work as fast as DRAM thanks to low read latency (i.e. ~100 ns) of NOR flash. It also does not need predictive software. Therefore, high performance could be maintained at all times. SLC NOR flash has high endurance thanks to the single-level cell (SLC). Therefore, NOR flash in DDR4 NVDIMM could replace DRAM, and boost system performance significantly with a large amount of main memory as shown in figure 3. If an affordable NOR flash could be generated through 3D NOR, DDR4 NVDIMM would be much more attractive. Second generation 3D XPoint (i.e. 4-ayer) is expected to be about half the cost of DRAM and has some mass production issues (see related story, 3D XPoint – Reality, Opportunity, and Competition). Conventional planar NOR is not as affordable because of the large cell size (i.e. about 10F2 to 12F2). Therefore, 3D NOR should be essential for DDR4 NVDIMM. In the case of 3D NOR, it could be 6 cents/GB (see related story, Will Storage Class Memory Disrupt Memory Hierarchy?).  Figure 3: DDR4 NVDIMM configuration along with 3D DRAM and 3D NOR. For 10GB 3D DRAM plus 1TB 3D NOR, the cost of DDR NVDIMM is to be $10+$60=$70. Today, the industry is being crippled by soaring DRAM prices, and is just waiting idly for next downturn. Many analysts consider this upturn to be just another boom time for DRAM, and anticipate the next downturn as the market balances out between supply and demand. However, at this time, we should consider more factors to predict the DRAM market in the future. If we look into the history of DRAM, the downturns came when DRAM bit growth was more than 45 percent and caused oversupply. Now, Moore’s Law does not work for planar DRAM anymore and bit growth will be the lowest it has been for the past 23 years. Because we cannot see more than 45 percent DRAM bit growth from planar DRAM, there will not be any downturn in the future. Certainly, 3D DRAM is not an option today because the technology is not there. NVDIMM using 3D NOR could significantly reduce the total ownership cost of memory subsystems, because 6 cents/GB of 3D NOR could replace DRAM and SSD at the same time as a main memory as well as storage memory. As we know, planar DRAM has not been changed at all for the last several decades. We must start innovating DRAM now.

https://www.eetimes.com/author.asp?section_id=36&doc_id=1332646